Logical device for comparing the phase shift of an electrical magnitude to be checked in relation to a reference electrical magnitude

ABSTRACT

Phase comparing process and device in which the alternations of both a reference electric magnitude and an electric magnitude to be checked are converted into rectangular pulses, then the rectangular pulse corresponding to the magnitude to be checked is derivated, in order to determine whether or not there exists a time coincidence between said derivative and each rectangular signal corresponding to the reference electric magnitude.

United States Patent Inventor Claude-Auguste Queron Seine, France Appl. No. 6,416

Filed Jan. 28, 1970 Patented Jan. 11, 1972 Assignee Compagnie Des Compteurs Paris, France Priority Jan. 28, 1969 France 6901613 LOGICAL DEVICE FOR COMPARING THE PHASE SHIFT OF AN ELECTRICAL MAGNITUDE TO BE CHECKED IN RELATION TO A REFERENCE ELECTRICAL MAGNITUDE 7 Claims, 10 Drawing Figs.

U.S. Cl 324/83 D Int. Cl G0lr 25/00 [50] Field of Search 324/83 A, 83 D; 328/1 10, 133

[56] References Cited UNITED STATES PATENTS 3,388,326 6/1968 Brooks 324/83 D 3,016,475 1/1962 Kirsten 324/83 D 3,271,675 9/1966 Kreinberg 324/83 D Primary Examiner-Alfred E. Smith Att0rney Pierce, Scheffler & Parker V %U( tonvevl'tv I l 2 V k A ND l'crn emry memory 4 PATENTED Jun 1 m2 SHEET 1 [IF 6' Pi 6.1V.

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devivnHve C Ycu 0- tonvevrer PATENTED JAN] 1 I972 SHEET 5 [1F 6 Fiat LoGrCALnEvICE FOR COMPARING THE PHASE surr'r OF AN ELECTRICAL MAGNITUDE TO BE CHECKED IN RELATION To A REFERENCE ELECTRICAL MAGNI'VIUDE In numerous applications, for instance, in metering relays or any other phase selector devices, it is often necessary to know the vectorial position of an electric magnitude in relation to one or more reference electric magnitudes, and to locate automatically this vectorial position in a precisely defined displacement zone.

Also, in certain cases, it is usefulto know permanently and with great accuracy, the phase displacement of an electric magnitude with respect to another one and in case to follow the phase displacement of the electric magnitude which is to be checked, for instance to enable the subsequent control of devices intended to bring said phase displacement within a given limit in relation to the phase of the reference magnitude.

The device of the invention comprises at least one converter forming rectangular pulses of the same width as one of the alternations of the reference electric magnitude, at least one converter forming rectangular pulses corresponding to one of the alternations of the electric magnitude to be checked, a derivating circuit connected to the converter of the electric magnitude to be checked and forming the derivative of the rectangular pulses coming from this converter, a coordination AND gate whose inputs are respectively connected to said converter of the reference electric magnitude and to the circuit of the pulses coming from the electric magnitude to be checked, and temporary memory means connected to the output of the AND gateand to the converter of the magnitude to be checked.

Various other characteristics of .the invention are moreover revealed by the detailed description which follows.

Embodiments of the invention are shown by way of nonrestrictive example, in the accompanying drawings.

FIG. 1 is an explanatory Fresnels diagram of the invention.

FIG. 2 is a logical diagram of an embodiment of the phase comparator device of the invention.

FIG. 3 is a set of explanatory curves for the working of the device of FIG. 2 with regard to the Fresnels diagram of FIG. 1.

FIG. 4 is a diagram of a logical circuit showing a development ofthe circuit of FIG. 2.

FIG. 5 is a diagram of a logical circuit showing a slight alternative as compared with FIG. 2.

FIG. 6 is a Fresnels diagram similar to FIG. 1, but showing an additional development of the invention.

FIG. 7 is a diagram of a logical circuit showing the embodiment of the device embodying the characteristics arising out of FIG. 6.

FIG. 8 is a set of curves showing the working of the logical circuit of FIG. 7 with regard to the Fresnels diagram of FIG. 6

FIGS. 9 and 10 are diagrams of logical circuits showing two developments of the circuit of FIG. 7.

FIG. 1 represents a Fresnels circle in which the vector V represents a reference alternating voltage V and V shown by a solid line represents a voltage V, whose phase displacement is to be watched in relation to the position of the phase of the voltage V,,. In the case considered and according to the usual conventions the voltage V lags with regard to the voltage V In the following disclosure, voltages only are dealt with, but it is quite obvious that there may be other electric magnitudes, and particularly currents whose phase displacement is to be determined or watched with regard to the phase of a reference current or of several reference currents.

Referring again at FIG. I and in the simple case when there only exists a single reference voltage V then it is advisable to ascertain whether'the phase displacement of the voltage V, is lagging or leading, in relation to the phase of the voltage V or, in other words, if the vector V is in the circular sector ADB. as shown by a solid line. or on the contrary in the circular sector BBC as shown by a dotted line in the hachurated zone.

To know whether the vector V, is in one or the other of the above-mentioned sectors of the Fresnels circle, and this by keeping a continual watch and detection in the time lag equal to a period of the alternating current or voltage, one proceeds as follows:

A shown on FIG. 2, one applies the voltages V and V,- to the input of converters l and 2, formed, par example, each one by a transistor of a thyristor controlled at the beginning of each alternation in order, as in the example considered in FIG. 2, to select only the positive alternations of the voltages V and V and to form, for each one of said positive alternations, a rectangular pulse V, of the same width as the alternation considered of the voltage V This is shown by the first curve of FIG. 3, where the distance AB corresponding to the width of the pulse V, corresponds to the vector V of FIG. 1, whereas the distance BC corresponds to the width of the negative pulse which is eliminated by the converter 1. In like manner, the converter 2 to which the voltage V is applied, produces, for each positive alternation, a rectangular pulse V,. This pulse is shown by the second curve of FIG. 3, which shows that this second pulse lags in relation to the pulse V,.

The pulses V, are successively applied to the input of a derivating circuit 3 which forms the derivative V of these pulses, i.e., as known in electricity, a short pulse which is shown on the third curve of FIG. 3, this short pulse being obviously formed at the same time that the pulse V, begins to occur. The output of derivating circuit 3, and the output of the converter 1, are connected to the inputs of a coincidence AND-gate 4, which itself is connected, by its output, to an input of a temporary memory 5, which can be made in numerous different ways, and, for instance, by a capacitance-resistance circuit associated with a Schmitt trigger. The memory 5 also receives at its input, the pulses V which are applied to it by a conductor 6 connected to the output of the converter 2. For instance, the memory 5 is provided so that its output S issues a continuous voltage or current signal of a given value when this memory does not receive any information from the AND gate and said memory is made, as is the case when it is formed by a resistance-capacitance circuit associated with a Schmitt trigger, so that the pulses V that can be directly applied to it do not alter its state, hence do not alter the signal that it supplies at its output 8,, but on the other hand that it is in a position to change of state, and thus to modify the signal at its output 8,, if a pulse comes from the AND gate.

Considering again the example of FIG. 1, corresponding to the set of curves of the bracket I of FIG. 3, in relation with the curve V of the reference voltage, one sees that at the moment when the pulse V, is formed, the derivating circuit 3 produces the pulse V, which is applied to one of the two inputs of the AND-gate 4. Moreover, the reference pulse V, is applied to the other input of the AND gate which is thus open, and consequently, the pulse V, is applied to the input of the memory 5 which rocks, so that the continuous signal which was coming from it is cancelled, as shown at S, on the last curve of the set of curves of the bracket I of FIG. 3. This new state of the memory 5, remains as long as the pulse V, is applied, upon which the memory 5 resumes its initial state and thus supplies again the signal of the predetermined value. The pulse V, is thus used as a time base.

Therefore, the same working operations are renewed at each repetition of the pulses V, and V, if the phase displacement of the voltage V does not vary in relation to the phase of the reference voltage V Consequently, this displacement is checked at each period.

FIG. 3 shows that the working conditions described above are identically repeated provided there is a time coincidence between the pulses V, and V,, i.e., provided the derivative pulse V, is produced during the time of the reference pulse V,, which is shown by the dotted line D. The position of this straight line D corresponds to the measure of the phase lag of the voltage V, in relation to the phase of the reference voltage V, and hence to the arc AD of FIG. I.

Seeing that it has been shown that the working conditions of the memory 5, i.e., in a still more simple way than the conditions for which the AND gate can be open, are identically reproduced, provided there is a coincidence between the pulse V nd the derivative pulse V',., then the are AD may be of any kind but comprised in the arc AB of FIG. 1.

If one now considers the set of curves of the bracket II of FIG. 3, still in relation to the reference voltage V one sees that the voltage V is lagging for more than 180 in relation to said reference voltage V or else, on the other hand, that it is leading for less than 180. In this case, as shown by the straight dotted line E, there is no longer any coincidence between the pulse V and the derivative pulse V',.. Consequently, one of the inputs of the AND-gate 4 is open as long as the pulse V, lasts, but the other input is not open during this time, so that said AND gate is never open. It follows that the pulse V when it occurs, is properly applied to the temporary memory 5, but the state of said memory is not modified, and consequently the signal at its output S is a continuous signal. In this case, one is thus assured that the vector V in dotted line in FIG. 1 is in the sector BEC at any of the points thereof, because these latter working conditions remain as long as there is no coincidence between the derivative signal V and the reference pulse V If, for any reason, the phase displacement of the voltage V varies abruptly and passes from one to the other of the two zones of the Fresnels circle of FIG. I, then this is determined in a time at the most equal to one period, simply by watching the output signal of the memory 5, signal which can be used for operating a protection device, for instance. It is obvious that the memory 5 can, if so required, be suppressed, the essential point being to ascertain whether there is, or not, a signal at the output of the AND gate, seeing that it is the existence of this signal which informs whether the vector V is on one side or the other of the reference vector V In some cases, it may be useful to determine again more quickly a phase displacement of an electric magnitude in relation to a reference magnitude, and to obtain continuous signals which are characteristic of overstepping a displacement threshold.

FIG. 4 shows how an embodiment of the invention enables to check at each alternation a phase displacement, at the same time as continuous signals of different levels are produced for two characteristic phase displacement conditions. In this embodiment, one simultaneously uses positive and negative alternations. To this end, the device firstly comprises the same means as those above described with reference to FIG. 2, these same means being shown by a solid line and given the same references. Furthermore, a new identical unit is provided, but whose converters l and 2,, which also respectively receive the reference voltage V and the voltage V to be checked, are provided for respectively forming pulses in dependency on the negative alternations of the voltages V and V For this reason, in FIG. 4 the different references are shown with signs and The unit receiving the alternations V and V works exactly as previously described with reference to FIG. 2, the other unit receiving the alternations V and V works, of course, in a similar manner, and consequently, the signals produced when there is a coincidence between the pulses V, nd the derivative pulses V, are respectively those of the bracketl of FIG. 3. However, seeing that the negative altemations are also analyzed, then by connecting the outputs S and Slof the memories 5 and 5,, there is obtained a continuous signal instead of a discontinuous one. If the phase displacement between the voltages V and V,. varies abruptly, this is detected either by the unit analyzing the alternations or by the unit analyzing the alternations so that the detection is then estimated in a time at the most equal to a half-period. This also applies if the working is that explained in relation to the bracket II of FIG. 3, but the signal level is then different. By providing the memories 5 and S with two outputs 8,, S and S", S2 respectively. and in connecting these outputs between them, one permanently obtains two distant logical data permitting, for the same reasons, the ascertainment that the phase of the voltage V, is shifted in front or behind in relation to the phase of the reference voltage V FIG. 5 shows an alternative logical diagram of FIG. 2, this alternative enabling the memory to be used as a single flip-flop 5a, In this case, the AND-gate 4 is connected, by its output, to one of the inputs e, of the flip-flop 5a, whereas the output of the derivating circuit 3 forming the derivative V, is connected, on the one hand, to one of the inputs of the AND-gate 4, and on the other hand, to the other input e of the flip-flop 5a by means of a resistance 7 or other attenuating member eventually associated with an inverter circuit. In this embodiment, it is no longer necessary to connect the output of the converter 2 to the memory, as was the case in FIG. 2. When there is a coincidence between the pulses V, and the derivative pulses Ve, then, as in the preceding examples, the AND gate 4 is open and a pulse is applied to the input 2, of the flipflop 5a. The derivative pulse V'c is also applied to the second input 2 of the flip-flop 50 at the same time as the pulse coming from the AND gate, but the level of this pulse is lower, seeing that it is applied across the resistance 7. In this way, the flipfiop 5a is made active on its hachured side and one obtains, at the outputs of said flip-flop, the logical states I and 0 which give knowledge of the state of the above-mentioned coincidence, hence that the vector V of FIG. I is in the sector AB. One therefore sees that for each positive alternation, there is a confirmation of the order on the input e, of the flip-flop 511. If at a given moment, the phase displacement of the voltage V means that the vector representing this voltage goes in the sector BC of FIG. I, which corresponds to the case of the set of curves of the bracket II of FIG. 3 then the AND gate cannot be open, and consequently, no order confirmation pulse is applied at the input e of the flip-flop. Consequently, the derivative pulse V, is applied to the input e and the logical state at the output of said flip-flop change abruptly.

In some cases, it is advisable, and even necessary, to know with accuracy the phase displacement of an electric mag nitude or else to locate said displacement in any number of sectors of the Fresnels circle. To illustrate what follows, FIG. 6 shows a Fresnels circle similar to FIG. I, but on which there are four sectors 01,3 y 5, in one of which must be determined where is the vector V To do this, as shown in FIG. 7, one uses two reference voltages V and V which are applied like the voltage V to be checked, as in the preceding examples, to converters l for the voltage V Ia for the voltage V and 2 for the voltage V The converters I, la are connected to a AND-gate 4a by means of NOT-gates 8, 8a which can be short circuited by means of derivating circuits 9, 9a provided with switches 10, 10a.

As in FIG. 2, the converter 2 receiving the voltage V to be checked, is connected to a derivating circuit 3 forming the derivating V,, this derivative circuit being itself connected to a third input E3 of the AND-gate 4a whose output is connected to one of the inputs of the memory 5. Also, as in FIG. 2, the second input of the memory 5 is connected to the output of the converter 2 receiving the voltage V For clearly understanding the working of the device according to FIG. 7, and taking as an example that the vector V is in the sector a (FIG. 6) it is firstly necessary to refer to FIG. 8 in which there is shown at III the reference voltage V at IV the reference voltage V at V the voltage to be checked V,., at VI the derivative pulses V'c coming from the derivating circuit 3, and at VII the signals supplied by the output S of the memory 5.

In the first place, one sees that the converters I, la and 2, respectively supply the rectangular pulses V V,-; and V,. If one considers that the voltage V, is taken as original voltage and that the voltage V is taken to be the limit voltage according to the Fresnels diagram of FIG. 6, then it is necessary that the phase displacement of the voltage V be comprised between the phase of the voltage V,,,, and the phase of the voltage V to find itself in the sector 0:, Le, between the limits A and B appearing both in FIG. 6 as well as in FIG. 8.

For verifying this working condition and taking into account what was explained in the foregoing, it is obviously necessary to obtain a state of coincidence so that the two inputs E, and E of the AND-gate 4a are open.

If the NOT-gates 8 and 8a are not taken into account, FIG. 8 shows that it is not possible to obtain this condition, because the reference vector V is, in the example chosen, necessarily shifted more to the rear than the vector V thereby showing the phase displacement to the rear of the voltage to be checked, in relation to the original voltage V,,,. Nevertheless, the device of FIG. 7, providing a NOT gate interposed between the AND gate and each of the converters l and 10, one sees that when closing the switch 10 of the derivating circuit 9, the NOT-gate 8, is isolated, i.e., that the pulse V,, is obtained for the input E, of the AND gate, and that on the contrary, by keeping the switch 10a open of the derivating circuit 9a, there is obtained, on the input E a complementary logical pulse V,, which appears in FIG. 7, as well as in mixed lines on the curve IV of FIG. 8, which, by this artifice, permits the opening of the input E of the AND-gate gate 4a.

In these conditions, the beginning of the pulse V, is seen giving rise to the derivative V which opens the third input E of the AND-gate 4a; this gate thus becomes passing, and, for the reasons explained in the foregoing, the memory 5 changes its state and shows, at its output 5,, during the entire time of the pulse V the characteristic signal S,,,.

The precedings may be put down in a simple manner in binary notation. Actually, for all the values of the phase displacement of the vector V in the sector a, the following relation must be effected, namely m' nz in which V shows that use is made of the NOT-gate 811. By utilizing the same binary notation, if it is desired to watch the phase displacement of the vector V, in the sector B, the following relation must be effected:

i.e., that the NOT-gates 8 and 8a are both short circuited by closing the switches 10 and 10a. This case can be verified by referring to FIG. 8 which clearly shows that in the space separating the dotted lines B and C, pulses V,, and V, are superimposed.

In like manner, with regard to the sector y, for verifying that the vector V is in said sector 7, the following relation must be effected m' m In other words, in this case, the NOT-gate 8 is used and the NOT-gate 8a is short circuited.

Finally, with regard to the sector 8, it is necessary to satisfy the relation:

ki nz which means that in this case, the two NOT-gates 8 and 8a are kept in the circuit.

In the example of FIG. 7, the memory is shown with two outputs S, and 8,, these two outputs obviously giving signals which are complementary between them and which are the image, during each period, of the sector in which the sector V is, in relation to the reference vectors V,,, and V taking into account the choice made of one or other of the sectors by putting into circuit, or on the contrary, out of circuit, one and/or the other of the NOT-gates 8 and 8a. Actually, it has just been explained that by putting the gate 8 out of circuit, one checks, at each period, that the vector V is in the sector a, that by putting the two gates 8 and 8a out of circuit, one checks that the vector V is in the sector ,8, by putting the gate 8a out of circuit, one checks the sector 'y and by putting the gates 8 and 8a out of circuit, one checks the sector 8.

As a consequence, when the position of the vector V is entirely unknown, it is easily possible to make a successive search of the various sectors by operating the switches 10 and 10a.

FIG. 9 shows an amplified development of the device with two reference voltages shown FIG. 7, this development making possible to adjust the arc of the sector, sector a for instance, defining two phase displacement thresholds which must not be passed in one direction or the other by the vector V representing the voltage to be checked. This development of the invention uses exactly the same means as those of FIG. 7, which have consequently the same reference numbers. In addition, there is introduced upstream, for example, of the converter 1a, a calibrated phase displacement circuit 11 (shown as (b). By this means, and referring, for instance, to FIG. 6, the reference voltage V being taken as the origin, and the phase of the reference voltage V being able to be regulated at will by the phase displacement circuit 11, it thus becomes possible to approach or remove the vector V, from the vector V,,, in order to give to the arc AB the required opening, which, if so desired, can be very small. It is obvious that a similar phase displacement circuit can also be mounted upstream of the converter 1. By knowing exactly the value of the phase displacement of one or other of the vectors V,,,, or V it then becomes possible to know with accuracy and eventually even to follow, the phase displacement of the vector V by only verifying that the AND-gate 4a is open, or on the contrary, closed at each period, or even if so required, at each half-period.

Another development also appears in FIG. 10 which shows that more than two reference voltages can be used. Actually, as shown in said Figure, reference voltages V,,,, V, ..V can be applied to converters 1, 1a ..ln each connected to a NOT-gate 8, 8a ..8n, whereas the voltage V is applied to the converter 2. Although different circuits can be considered, it is often advantageous, as shown by the drawing, to consider the voltage V,,, as an original voltage, and consequently, the NOT-gate 8 is connected directly to one of the inputs E, of the AND-gate 4a, of which the other input E can be selectively connected, by a switch 12, to the NOT-gates 8a ..8n, the third input E of said gate 4a being connected to the derivating circuit 3. The NOT gates belonging to the various reference voltages, are also provided with their derivative circuits 9, 9a ..9n

By means of this embodiment and, as shown by the preceding explanations, it is possible to multiply the number of sectors a ,6.....of the Fresnels circle as much as desired and, by acting on the switch 12 it is possible to choose the position of the reference vector V defining, with the original reference vector V,,,, a sector with the desired angular opening. If so required, by acting on the switch 12 on the one hand, and on the other hand on the switches 10, 10a ..l0n in a sequential manner, it becomes possible to scan the whole of the Fresnels circle.

Iclaim: I

1. A logical device for comparing the phase-shift of an electric magnitude to be checked in relation to at least one reference electric magnitude, both said electric magnitudes having same frequency, wherein said device comprises a first converter connected to the electric magnitude to be checked and forming therefrom rectangular pulses of a same width as one alternation thereof;

at least one second converter connected to the reference electric magnitude and forming therefrom rectangular pulses of a same width as one alternation thereof;

a derivating circuit connected to the first converter and forming the derivative of the rectangular pulses from the electric magnitude to be checked:

a coincidence AND gate having at least one set of at least two inputs, said two inputs being respectively connected to said at least one second converter and to the derivating circuit;

a temporary memory having two complementary outputs and at least one set of at least two inputs, one of said two inputs being connected to the output of the coincidence AND gate to be controlled thereby,

the other one input of said two input temporary memory being connected to the output of the first converter; whereby the rectangular pulse signal coming from said first converter is controlled by a signal coming from the coincidence AND gate, so that the position of the electric magnitude to be checked is known with respect to the position ofthe at least one reference magnitude.

2. A device according to claim 1 characterized in that the temporary memory is made in the form of a resistancecapacitance circuit associated with a two-input Schmitt trigger, of which one input is connected to the output of the converter connected to the electric magnitude to be checked, so that the rectangular pulses coming from this converter are used both for the unlocking of said trigger and as a time base for it, and the other one of the two inputs of said trigger being connected to said AND gate, whereby the output of said trigger supplies a continuous signal when the derivative of the signal coming from the electric magnitude to be checked does not coincide with the pulse coming from the reference electric magnitude, and that said output of the trigger supplies a periodical signal, of the same frequency as said electric magnitudes when the derivative coming from the magnitude to be checked coincides in time with a pulse coming from the reference magnitude and makes said AND gate, gate passing.

3. A device according to claim 1, characterized in that the temporary memory is formed by a two-input bistable flip-flop of which one input is connected to the output ofthe AND gate and of which the other input is connected, by an attenuating member, to the output of the derivating circuit, whereby said bistable flip-flop is kept in a same logical state as long as the derivative coming from the magnitude to be checked is in coincidence with the pulse coming from the reference magnitude and that said flip-flop is brought into the other logical state when there is no more this state of coincidence and that the signal coming from the derivative circuit is applied to it.

4. A device according to claim 1, wherein the first converter and the at least one second converter have each one two inputs respectively tuned on the positive alternations and on the negative alternations of the electric magnitude to which they are connected; and wherein the coincidence AND gate and the memory means each has a first and a second sets of at least two inputs, said first and second sets being respectively related to said positive and negative alternations.

5. A device according to claim 1, characterized in that it comprises at least two converters respectively connected to a reference electric magnitude and said converters are each connected to an input of a three-input coincidence gate, by means of NOT gate associated to the derivating circuits, the third input of said coincidence gate being connected to the output of the derivating circuit connected to the converter, to which is applied the electric magnitude to be checked, whereby said converters receiving the reference electric magnitudes form two trains of rectangular pulses, phase shifted in relation to one another by a known extent, thus defining, in a Fresnel's diagram, four distinct sectors, the situation of the vector corresponding to the dephasing of the magnitude to be checked being determined by the opening of the coincidence gate and the putting into or out of circuit of said NOT gates interposed between said coincidence gate and said converters corresponding to said reference magnitudes.

6. A device according to claim 1, characterized in that a calibrated dephasing circuit is placed upstream of at least one of the converters corresponding to the reference magnitudes, so that the sectors defined by the representative vectors of the respective phases of said reference magnitudes are adjustable in the Fresnels diagram for modifying the arc of said sectors in one direction or the other.

7. A device according to claim 5, characterized in that it comprises more than two converters respectively connected to a reference electric magnitude, said converters associated with their NOT gates being connected to the coinciding AND gates by a selector switch.

Patent No. 624,762

Inventofls) It is certified tna-tjerror appe'ars in the above-identified patent and that said Letters Patent :are hereby corrected as shownv below:

In trite Specification:

col. 15.218 49, derfiatin should be Q 'shunting w 001.. iinc l3 ahd l6, "derivating" shculd be I v shunting Co l 6, line; 37, "derivating" should be v I I {shaming In the" Claimsy E01. 7, iineQO, gate" should be cancelled Col. 8 iine 9 'g ate asisociated to the deriyiating I I circuitc should be gates having shunting circuits associated theremth Signed and scaled this 27th day of June 1972,

(SEAL) Attest: EDWARD MQFLETCHER,JR. ROBERT GOTTSCH'ALK Attescihg Officer Commissioner of Patents Y 

1. A logical device for comparing the phase-shift of an electric magnitude to be checked in relation to at least one reference electric magnitude, both said electric magnitudes having same frequency, wherein said device comprises a first converter connected to the electric magnitude to be checked and forming therefrom rectangular pulses of a same width as one alternation thereof; at least one second converter connected to the reference electric magnitude and forming therefrom rectangular pulses of a same width as one alternation thereof; a derivating circuit connected to the first converter and forming the derivative of the rectangular pulses from the electric magnitude to be checked: a coincidence AND gate having at least one set of at least two inputs, said two inputs being respectively connected to said at least one second converter and to the derivating circuit; a temporary memory having two complementary outputs and at least one set of at least two inputs, one of said two inputs being connected to the output of the coincidence AND gate to be controlled thereby, tHe other one input of said two input temporary memory being connected to the output of the first converter; whereby the rectangular pulse signal coming from said first converter is controlled by a signal coming from the coincidence AND gate, so that the position of the electric magnitude to be checked is known with respect to the position of the at least one reference magnitude.
 2. A device according to claim 1 characterized in that the temporary memory is made in the form of a resistance-capacitance circuit associated with a two-input Schmitt trigger, of which one input is connected to the output of the converter connected to the electric magnitude to be checked, so that the rectangular pulses coming from this converter are used both for the unlocking of said trigger and as a time base for it, and the other one of the two inputs of said trigger being connected to said AND gate, whereby the output of said trigger supplies a continuous signal when the derivative of the signal coming from the electric magnitude to be checked does not coincide with the pulse coming from the reference electric magnitude, and that said output of the trigger supplies a periodical signal, of the same frequency as said electric magnitudes when the derivative coming from the magnitude to be checked coincides in time with a pulse coming from the reference magnitude and makes said AND gate, gate passing.
 3. A device according to claim 1, characterized in that the temporary memory is formed by a two-input bistable flip-flop of which one input is connected to the output of the AND gate and of which the other input is connected, by an attenuating member, to the output of the derivating circuit, whereby said bistable flip-flop is kept in a same logical state as long as the derivative coming from the magnitude to be checked is in coincidence with the pulse coming from the reference magnitude and that said flip-flop is brought into the other logical state when there is no more this state of coincidence and that the signal coming from the derivative circuit is applied to it.
 4. A device according to claim 1, wherein the first converter and the at least one second converter have each one two inputs respectively tuned on the positive alternations and on the negative alternations of the electric magnitude to which they are connected; and wherein the coincidence AND gate and the memory means each has a first and a second sets of at least two inputs, said first and second sets being respectively related to said positive and negative alternations.
 5. A device according to claim 1, characterized in that it comprises at least two converters respectively connected to a reference electric magnitude and said converters are each connected to an input of a three-input coincidence gate, by means of NOT gate associated to the derivating circuits, the third input of said coincidence gate being connected to the output of the derivating circuit connected to the converter, to which is applied the electric magnitude to be checked, whereby said converters receiving the reference electric magnitudes form two trains of rectangular pulses, phase shifted in relation to one another by a known extent, thus defining, in a Fresnel''s diagram, four distinct sectors, the situation of the vector corresponding to the dephasing of the magnitude to be checked being determined by the opening of the coincidence gate and the putting into or out of circuit of said NOT gates interposed between said coincidence gate and said converters corresponding to said reference magnitudes.
 6. A device according to claim 1, characterized in that a calibrated dephasing circuit is placed upstream of at least one of the converters corresponding to the reference magnitudes, so that the sectors defined by the representative vectors of the respective phases of said reference magnitudes are adjustable in the Fresnel''s diagram for modifying the arc of said sectors in one direction or the other.
 7. A device according to clAim 5, characterized in that it comprises more than two converters respectively connected to a reference electric magnitude, said converters associated with their NOT gates being connected to the coinciding AND gates by a selector switch. 